Field of the Invention
The present invention relates to an apparatus for Charged Device Model (CDM) testing, which is a specific form of Electro Static Discharge (ESD) testing. More specifically, the present invention relates to a CDM tester utilizing a high speed impedance transformer to control discharge impedance and to transform impedance test pulses of the complete time domain test waveform.
Description of the Related Art
The Charged Device Model (CDM) test was devised to simulate a real world threat when an Integrated Circuit (IC) chip has acquired a charge, such as, for example, the triboelectric charge that builds up a voltage on the IC chip as the chip slides down metal chutes during normal machine handling. In the CDM test, the Device Under Test (DUT) is charged to a specific voltage that is expected to be found in the manufacturing or assembly environment.
During IC chip handling or movement, one of its many leads or pins will come in contact with a metal surface of zero charge. This causes the charge in the package and silicon chip to flow out through that one metal lead. When the charge voltage is above about 300 volts, the discharge process typically develops an air-spark discharge. At lower charge voltages, the air discharge rarely forms and a direct metal-to-metal contact provides the discharge current path.
The time for the discharge current to rise to its peak for charge voltages as low as 100 volts has been measured as being less than 30 picoseconds. It is very fast but is of very brief duration—only a few nanoseconds. These time parameters define the measurement speeds found in CDM testing.
The CDM test also has a specific parameter different from other Electrostatic Discharge (ESD) tests and real world ESD threats. The discharge resistance of low voltage discharges between metal contacts or air ionization between the contacts is the lowest of any ESD test. Simulating the real world threat to the packaged device in a test is critical to provide a reliable test.
The present Charged Device Model (CDM) test uses a one-ohm resistor in the discharge path to ground as a current-sensing resistor. It was originally designed to measure or record the discharge current waveform on a 1 GHz oscilloscope. The risetime measurement limit for this oscilloscope is about 350 picoseconds. The one-ohm resistance value was chosen to be low enough to not add significantly to the combined resistance of the device and spark resistance. The current-sensing resistor monitors the current flow out of an integrated circuit during the discharge. The current-sensing resistor provides high bandwidth response for analysis of high-speed discharge current data. Recent advances in oscilloscope bandwidth to 6 GHz increases its risetime measurement limit to about 60 picoseconds. These higher speeds have increased the waveform data information for improved ESD protection circuit design and analysis. To insure future measurement speeds of less than 30 picoseconds, test bandwidths for both measurements and test pulses ideally should be at least 10 GHz. This will insure accurate test simulations and current discharge waveform data capture information.
Diode and other ESD silicon voltage clamps are used where the connection leads, pins, or balls connect to the silicon chip, to protect the chip's operating circuits. This CDM type of ESD event can be fast enough that silicon ESD protection circuits may not turn on sufficiently fast to protect sensitive gate oxides in modern complementary metal-oxide-semiconductor (“CMOS”) circuits. A 10-picosecond turn-on delay in protection operation may not clamp the early part of the ESD threat. This will allow some of the ESD voltage to not be fully clamped by the protection circuit, which can damage sensitive gate oxides in the operating part of the IC chip.
The CDM current discharge flows through the spark or metal contact to the ground return. Unfortunately, air sparks and metal-to-metal contacts have variable resistances, which cause the measured discharge current to also vary. A no-spark method of CDM testing has been sought for many years. A new Contact CDM (“CCDM”) test is being considered to eliminate discharge pulse amplitude variations.
A 50-ohm CCDM tester has been proposed as a sparkless CDM test solution. The device pins to be tested are connected via a 50-ohm transmission line to a high-speed switch connected to a voltage supply to charge the assembly to specific voltage test levels. When the switch is closed, it discharges the transmission line and the DUT into a 50-ohm load or an attenuator. Test data with the 50-ohm load impedance have produced peak currents significantly lower than that of the existing CDM tester. Testing at the same voltage but increasing the peak current to match that of the CDM test will require reducing the CCDM source or load impedance until it matches the discharge impedance of the CDM test. It has been suggested that the spark resistance part of the discharge load impedance may be 25 ohms. However its true value may be even lower and is best determined by measurement.
Any new test to improve peak current repeatability must also provide the same CDM threat to the Device Under Test (DUT). If the sparkless CCDM CDM tester is to provide the same ESD threat to the DUT, its source impedance that replaces the discharge spark or contact is an important factor in providing the same peak current. The peak discharge current is determined by the combination of the device internal circuit impedance, the CDM tester's spark, or contact resistance, and the one-ohm current sensor. For the new test to replicate the CDM test and provide the same discharge current threat, its source impedance must be the same as the spark or contact impedance or resistance which it replaces.
Certain Japanese companies provide a CCDM test method using a short conductor connecting the DUT pin to be tested. The conductor and the pin are charged to the test voltage, and both are connected to a controlled atmosphere switch. This CCDM test closes the switch to discharge the short conductor and the DUT into a low resistance resistive load. This Japanese CCDM method does not control the impedance of the short conductor or the impedance of the switch in the sub nanosecond time frame. The CDM failure level data does not correlate well with this CCDM test because the high speed impedance of the discharge path is not controlled to simulate the short path CDM discharge impedance.